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Silicon Labs /EFR32MG22C224F512IM32 /CMU_S /EUART0CLKCTRL

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Interpret as EUART0CLKCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)CLKSEL

CLKSEL=DISABLED

Description

No Description

Fields

CLKSEL

Clock Select

0 (DISABLED): UART is not clocked

1 (EM01GRPACLK): EM01GRPACLK is clocking UART

2 (EM23GRPACLK): EM23GRPACLK is clocking UART

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data